In context: TSMC and the Rising Costs of Advanced Semiconductor Nodes
The Commercial Times recently reported that TSMC’s upcoming N2 2nm semiconductors will come at a hefty price tag of $30,000 per wafer, marking a significant price increase compared to the company’s 3nm chips. This trend of escalating prices for cutting-edge semiconductor processes has raised concerns about the continued viability of Moore’s Law.
TSMC has justified these price hikes by pointing to the substantial costs associated with building 2nm fabrication plants, which can run upwards of $725 million. Despite the higher prices, major players like Apple, AMD, Qualcomm, Broadcom, and Nvidia are expected to place orders for TSMC’s 2nm chips, potentially filling up the company’s Arizona fab to full capacity.
Also see: How profitable are TSMC’s nodes: crunching the numbers
Among the first to benefit from TSMC’s N2 process is Apple, which is set to incorporate the A20 processor based on the 2nm technology in the upcoming iPhone 18 Pro. Additionally, Intel’s Nova Lake processors, designed for desktops and high-end laptops, are also slated to leverage the N2 process and are expected to hit the market next year.
Recent reports indicate that TSMC has made significant progress with its 2nm process, achieving yield rates of over 90% for 256Mb SRAM. With trial production likely underway and mass production scheduled to commence later this year, TSMC aims to produce tens of thousands of wafers by the end of 2025.
TSMC’s roadmap extends beyond the N2 process, with plans for N2P and N2X in the pipeline for the second half of next year. N2P is expected to deliver an 18% performance boost over N3E at the same power level, along with 36% greater energy efficiency and higher logic density. Meanwhile, N2X, scheduled for mass production in 2027, aims to increase maximum clock frequencies by 10%.
As semiconductor geometries continue to shrink, power leakage becomes a critical issue. TSMC’s 2nm nodes address this challenge with gate-all-around (GAA) transistor architectures, enabling more precise control of electrical currents.
In the pursuit of even smaller process nodes, TSMC is looking towards the Angstrom era, where technologies like backside power delivery will further enhance performance. Future nodes such as A16 (1.6nm) and A14 (1.4nm) could come with a hefty price tag of up to $45,000 per wafer.
Meanwhile, Intel is striving to keep pace with TSMC’s advancements, with the company already in the risk production phase of its A18 node. Featuring gate-all-around and backside power delivery technologies, these chips are expected to debut later this year in Intel’s upcoming laptop CPUs under the codename Panther Lake.
